High-Performance Deep SubMicron CMOS Technologies with Polycrystalline-SiGe Gates

The use of polycrystalline SiGe as the gate material for deep submicron CMOS has been investigated. A complete compatibility to standard CMOS processing is demonstrated when polycrystalline Si is substituted with SiGe (for Ge fractions below 0.5) to form the gate electrode of the transistors. Performance improvements are achieved for PMOS transistors by careful optimization of both transistor channel profile and p-type gate workfunction, the latter by changing Ge mole fraction in the gate. For the 0.18 ¿m CMOS generation we record up to 20% increase in the current drive, a 10% increase in the channel transconductance and subthreshold swing improvement from 82 mV/dec to 75 mV/dec resulting in excellent ¿on¿/¿off¿ currents ratio. At the same time, NMOS transistor performance is not affected by gate material substitutio

Degradation of Si MOSFET gate oxides by ion implantation

\u3cp\u3eWe have characterised the effects of ion implantation in advanced MOSFETs, and have shown that severe gate oxide degradations can be induced by ion implantations used routinely in front-end processing of MOS transistors. The mechanisms of oxide degradation are revealed to be connected to the nuclear energy transfer to the O atoms in the oxide during implantation. Si and O ion mixing can result in significant increase of the effective oxide thickness which also result in intrinsic device performance degradation.\u3c/p\u3

High-performance deep submicron MOSTs with polycrystalline-(Si,Ge) gates

\u3cp\u3eHigh-performance poly-Si\u3csub\u3e0.7\u3c/sub\u3eGe\u3csub\u3e0.3\u3c/sub\u3e gate PMOST and NMOST, compatible with conventional CMOS processing, are manufactured for devices with L\u3csub\u3eeff\u3c/sub\u3e down to 0.15 μm. For PMOST we observe a approximately 20% increase in saturation current and improved subthreshold slope from 81 mV/dec to 75 mV/dec while off-state currents and short-channel effects are comparable to conventional devices. No influence of poly-Si\u3csub\u3e0.7\u3c/sub\u3eGe\u3csub\u3e0.3\u3c/sub\u3e on the performance of NMOS transistors gates is observed.\u3c/p\u3

2D dopant profiling of advanced CMOS technologies by preferential etching, comparison with 2D process simulations

\u3cp\u3eIn this paper the possibilities for quantitative determination of 2D dope profiles in advanced CMOS technologies are investigated using selective etching in combination with TEM, SIMS and AFM. Promising results were obtained for As. For B an etch-rate dependence on the steepness of the B concentration gradient and influence of the background channel doping (As and P) seem to trouble quantification. A comparison between the measured and simulated (TSUPREM4) 2D profile of a 0.18ìm NMOST is presented.\u3c/p\u3

Gate-workfunction engineering using poly-(Si,Ge) for high-performance 0.18 μm CMOS technology

\u3cp\u3eWe show that poly-SiGe can be readily integrated as a gate material into an existing CMOS technology to achieve significant increase in the transistor performance. In order to preserve the standard salicidation scheme, a buffer poly-Si layer is introduced in the gate stack. PMOST channel profiles are optimized to account for the change of the gate workfunction. High-performance CMOS 0.18 μm devices are manufactured using p- and n-type poly-Si/Si\u3csub\u3e0.8\u3c/sub\u3eGe\u3csub\u3e0.2\u3c/sub\u3e gates.\u3c/p\u3

A manufacturable sub-50nm PMOSFET technology

\u3cp\u3eOne of the major problems during the processing of PMOS devices is the excessive diffusion of boron source and drain regions. Plasma enhanced CVD can be used to reduce the thermal budget associated with layer depositions between source/drain implants and back end. It also gives a possibility to selectively etch deposited layers to allow novel processing sequences. Here we study these possibilities and show that by using highquality PECVD depositions, we can engineer the appropriate for sub-50nm generation PMOS device architectures.\u3c/p\u3

Gate current and oxide reliability in p\u3csup\u3e+\u3c/sup\u3e poly MOS capacitors with poly-Si and poly-Ge\u3csub\u3e0.3\u3c/sub\u3eSi\u3csub\u3e0.7\u3c/sub\u3e gate material

\u3cp\u3eFowler - Nordheim (FN) tunnel current and oxide reliability of PMOS capacitors with a p\u3csup\u3e+\u3c/sup\u3e polycrystalline silicon (poly-Si) and polycrystalline germanium-silicon (poly-Ge\u3csub\u3e0.3\u3c/sub\u3eSi\u3csub\u3e0.7\u3c/sub\u3e) gate on 5.6-nm thick gate oxides have been compared. It is shown that the FN current depends on the gate material and the bias polarity. The tunneling barrier heights, φB, have been determined from FN-plots. The larger barrier height for negative bias, compared to positive bias, suggests that electron injection takes place from the valence band of the gate. This barrier height for the GeSi gate is 0.4 eV lower than for the Si gate due to the higher valence band edge position. Charge-to-breakdown (Q\u3csub\u3ebd\u3c/sub\u3e) measurements show improved oxide reliability of the GeSi gate on of PMOS capacitors with 5.6 nm thick gate oxide. We confirm that workfunction engineering in deepsubmicron MOS technologies using poly-GeSi gates is possible without limiting effects of the gate currents and oxide reliability.\u3c/p\u3

Gate polysilicon optimization for deep-submicron MOSFETs

\u3cp\u3eThe use of amorphously deposited silicon and fine-grained polysilicon as MOS gate material is discussed. A variety of deposition and anneal conditions was evaluated on MOS capacitors and transistors. Gate depletion and MOSFET matching have been studied as a function of deposition condition and gate activation temperature. It is shown that polysilicon gate material has better properties than α-Si for CMOS generations beyond 0.18μm.\u3c/p\u3

Channel profile engineering of 0.1 μm-Si MOSFETs by through-the-gate implantation

\u3cp\u3eA novel approach to the SSR channel profile formation for MOSFETs is suggested, with dopant implantation in the late stages of the processing, with the gate, source/drain already in (`TGi'). Only a single damage/activation anneal and the back-end thermal budget are experienced by the implanted dopants, which results in steep profiles even when light boron ions are used. High-performance NMOS devices with excellent SCE control designed for low-voltage digital, analog and RF operation were realized using this technique. For PMOS the use of TGi is restricted by significant diffusion of source/drain extensions due to the TGi damage induced TED.\u3c/p\u3

Dopant profile engineering of advanced Si MOSFET's using ion implantation

\u3cp\u3eIon implantation has been used to realize non-uniform, steep retrograde (SR) dopant profiles in the active channel region of advanced Si MOSFET's. After defining the transistor configuration, SR profiles were formed by dopant implantation through the poly crystalline Si gate and the gate oxide (through-the-gate, TG, implantation). The steep nature of the as-implanted profile was retained by applying rapid thermal annealing for dopant activation and implantation damage removal. For NMOS transistors, TG implantation of B yields improved transistor performance through increased carrier mobility, reduced junction capacitances, and reduced susceptibility to short-channel effects. Electrical measurements show that the gate oxide quality is not deteriorated by the ion-induced damage, demonstrating that transistor reliability is preserved. For PMOS transistors, TG implantation of P or As leads to unacceptable source/ drain junction broadening as a result of transient enhanced dopant diffusion during thermal activation.\u3c/p\u3